In a conventionally proposed configuration of a liquid crystal display device, in order to maintain the voltage applied to a pixel electrode, a storage capacitance wiring is provided to form a storage capacitance at a location where the storage capacitance wiring overlaps the pixel electrode. FIG. 37 shows a skeleton framework of an active matrix substrate, illustrating an example of such a configuration. In this illustrated configuration, a storage capacitance wiring 38 is disposed in parallel with the scan signal line 32, and a storage capacitance is formed where the storage capacitance wiring 38 and a pixel electrode 39 overlap. In this configuration, however, the storage capacitance wiring 38 is formed in the same layer as the scan signal line 32. As a result, a gate insulating film, which is an insulating film for the scan signal line 32 and the storage capacitance wiring 38, and an interlayer insulating film, which is an insulating film for a data signal line formed on the gate insulating film, are present between the storage capacitance wiring 38 and the pixel electrode 39. Consequently, a sufficient storage capacitance value cannot be obtained at a location where the storage capacitance wiring 38 overlaps the pixel electrode 39. Also, in order to obtain a greater capacitance value, the line width of the storage capacitance wiring 38 could be increased, but such configuration lowers the aperture ratio.
An example of the technology that can solve the problem is disclosed in Patent Document 1. Patent Document 1 discloses a liquid crystal display device (see FIG. 38) that includes a storage capacitance wiring disposed in parallel with the data signal line.
As shown in FIG. 38, for the active matrix substrate disclosed in Patent Document 1, a storage capacitance wiring 8 is formed on the gate insulating film, and an interlayer insulating film is formed on the storage capacitance wiring 8. As a result, only the interlayer insulating film is present between the storage capacitance wiring 8 and the pixel electrode 9. That is, in comparison to the configuration shown in FIG. 37, the distance between the storage capacitance wiring 8 and the pixel electrode 9 can be shortened by the amount equivalent to the film thickness of the gate insulating film. Consequently, if the area of the overlapping portion of the storage capacitance wiring and the pixel electrode is the same in the configurations of FIG. 37 and FIG. 38, the configuration of FIG. 38 can provide a larger storage capacitance. If the storage capacitance value is the same in the configurations of FIG. 37 and FIG. 38, the configuration of FIG. 38 can provide a thinner storage capacitance wiring, which increases the aperture ratio.
As discussed above, in comparison with the case in which the storage capacitance wiring is disposed in parallel with the scan signal line, in the configuration where the storage capacitance wiring is arranged in parallel with the data signal line, the storage capacitance value can be increased without sacrificing the aperture ratio.